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TRANSISTOR-CAPACITOR INTEGRATED CIRCUIT STRUCTURE Filed April 7, 1966 6Sheets-Sheet 6 O u u M MM 2 E 9' Q Q L) Q, Ru LL Lk k I United StatesPatent 3,383,570 TRANSISTQR-CAPACITOR INTEGRATED CIRKJUIT STRUCTUREJakob Liisclier, Carouge, Geneva, Switzerland, assignor to SocieteSuisse Pour llndustrie Horlogere S.A., Geneva, Switzerland, a Swiss bodycorporate Continuation-impart of application Ser. No. 441,975, Mar. 23,1965. This application Apr. 7, 1966, Ser. No. 540, 999 Claims priority,application Switzerland, Apr. 9, 1965, 5,031/65 9 Claims. (Cl. $17-$35)AESTRACT OF THE DISCLOSURE The invention provides an electronic circuitwhich can both be readily integrated and be of very low powerconsumption and in which circuit the active components consistessentially of insulated-gate field-effect transistors of sameconductivity type and the passive components consist essentially ofcapacitors, the integrated circuit being featured by at least oneelementary voltage-amplifying circuit having therein a pair of saidtransistors and a said capacitor, and supplied by a periodic voltagesource.

This application is a continuation-in-part of my application Ser. No.441,975, filed Mar. 23, 1965.

The present invention relates to a low power consumption integratedelectronic circuit.

According to the present invention there is provided an integratedelectronic circuit consisting essentially of insulated-gate field-effecttransistors of the same conductivity type and of capacitor structureelectrically connected in a predetermined circuit arrangement, each ofsaid transistors having first and second electrodes in a conductionpath, and a gate electrode for controlling the conductivity of the path,said electrodes being formed on one face of a body of semi-conductivematerial and said first and second electrodes of the transistors havingrectifying junctions with said body, and said capacitor structureincluding a capacitor having first and second electrodes and adielectric between said first and second electrodes thereof, saidcapacitor electrodes and dielectric also being formed on said one faceof said body, there being a voltageamplifying elementary circuit havingtherein a pair of said transistors and said capacitor, the firstelectrodes of said pair of transistors and of said capacitor beingconnected V to one another, the second electrodes of one of said pair oftransistors and of said capacitor being adapted to be connected to theterminals of a periodic supply voltage source, the gate electrode andthe second electrode of said one transistor providing the input of saidvoltageamplifying elementary circuit and being adapted to be connectedto the terminals of a control voltage source, the gate electrode of theother of said pair of transistors being connected to the secondelectrode of said capacitor, and the second electrodes of said pair oftransistors being in the output of said voltage-amplifying elementarycircuit.

The circuit according to the present invention is an improvement in thecircuits disclosed in my application Ser. No. 441,975 insofar as thevoltage-amplifying elementary circuit is able rapidly to charge, whennecessary, in the absence of a control (input) voltage to the gate ofits first transistor, a capacitor of low capacitance to a voltage havinga value very close to the maximum value of the voltage appearing at theoutput of the elementary circuit, and for this capacitor to remaincharged until the appearance of a control voltage of sufiicient value.

Identification of drawings In the accompanying drawings:

FIGURE 1 shows the electrical arrangement of a voltage-amplifyingelementary circuit which according to the present invention isintegrated;

FIGURE 2 shows, in perspective, the circuit of FIG- URE 1 in integratedform;

FIGURE 3 is a section along line III-III of FIG- URE 2;

FIGURES 4 and 5 are two explanatory graphs in connection with theelementary circuit of FIGURE 1;

FIGURE 6 is an electrical diagram of a first bistable set-reset circuit,which circuit includes two elementary circuits according to FIGURE 1;

FIGURE 7 is an electrical diagram of a second bistable set-resetcircuit, which circuit includes one elementary circuit according toFIGURE 1;

FIGURES 8, l0 and 12 is an electrical diagram of three differentfrequency dividing circuits, each including one elementary circuitaccording to FIGURE 1;

FIGURES 9a to 9e, 11a to 11 and 13a to 13!: show sixteen explanatorygraphs in connection with FIG URES 8, l0 and 12;

FIGURE 14 is an electrical diagram of a multi-stage frequency divider;and

FIGURES 15a to 15e show six explanatory graphs in connection with theFIGURE 14 circuit.

Disclosure of embodiments The voltageamplifying elementary circuit shownin ZGURE 1 comprises a first insulated-gate field-effect transistor T,which is connected, in series with a capacitor C to a source S supplyinga driving periodic voltage v Point I, which couples an electrode 1 oftransistor T and an electrode 3 of capacitor C is connected to anelectrode 5 of a second transistor T whose other electrode 6 isconnected to the output 7. The gate electrode 8 of transistor T isconnected to an input 10, whereas the gate electrode 9 of transistor Tis connected to source 8,. The second electrode 2 of transistor T isearthed.

FIGURE 2 shows the abovedescribed elementary circuit in integrated form.It is formed on one face of a semiconductive monocrystal which, in thepresent instance, is a monocrystal 11 of N-type silicon. The electrodesof transistors T and T 2 and one electrode of capacitor C are formed byP-type zones diffused into the crystal 11. The electrode 1 of transistorT the electrode 5 of transistor T and the electrode 3 of capacitor C areformed by a common Zone 135. The second electrode 2 of transistor T isformed by zone 2, with the second electrode 6 of transistor T beingformed by zone 6. Three other zones 12, 13 and 14 are moreover formed inthe same face of monocrystal 11 but are of N -type. The function of zone12 is to enable the earthing of crystal 11 and the function of zones 13and 14 being to prevent the build-up of inversion zones beneath thetransistor gate connections. On the silicon oxide insulating layer 15are deposited metallic layers which provide the gates 8 and 9 oftransistors T and T and the second electrode 4 of capacitor 0,. Anotherlayer 16 provides the ohmic contact for zones 2 and 12 to earth theelectrode 2 of transistor T and the monocrystal 11.

The above-described elementary circuit operates as follows:

In order that this operation may more readily be understood,consideration will first =be given to the part made up of transistor Tand of capacitor C i.e. without transistor T to see what voltage .vwould be in relation to the input (control) voltage v It will be assumedthat source S delivers unidirectional trapezoidal voltage impulses, asshown in FIGURE 4,

and that the threshold voltage of transistor T is larger than that ofthe PN junction formed by zone 135 with monocrystal 11. If the control(input) voltage V, is zero, the output voltage V then practically variesbetween and V because of the eltect of this junction PN, andcorresponds, as regards shape, to voltage v (see curve X in FIGURE 5).If voltage v is now applied and is progressively increased, voltage vwill progressively decrease and its shape will progressively change asshown by curves Y and Z in FIGURE 5. In view of this change in the shapeof voltage V various circuit amplification factors can be defineddepending on whether it is the peak value, the mean value or theeffective value of voltage v that is being referred to.

In the following, reference will be had to the peak value which is themost important for the operation of electronic circuits comprising oneor more elementary circuits.

Under current saturation conditions for transistor T this peak value is1 wherein dz) K, A I T t, and

I,=K(V,,V,,,) V being the threshold voltage of transistor T and K beinga constant which depends on the geometry of transistor T To obtain V =0,it is necessary to have I =AC such being the case when the controlvoltage v will at By carefully choosing values A, C, and K, it ispossible to arrange for this value of v to be much smaller than that ofvoltage v The circuit will now be considered as a whole, i.e. includingtransistor T Moreover, it will be assumed that a capacitor C shown indotted lines and having a capacitance much smaller than that ofcapacitor C is connected to the output 7 of the circuit.

If it is supposed that voltage V is zero and that the capacitor C isdischarged, a voltage v impulse will then as a result give rise to avoltage ,v having practically the same value as v and will moreover giverise to a control voltage for transistor T across its gate 9 and itselectrode 6 which forms its source. This transistor T 2 will thus berendered conductive, thereby causing capacitor C to be charged by theoutput voltage v whose maximum value will amount to the differencebetween V and V (the threshold voltage of transistor T When this maximumvalue of V will have been reached, transistor T will be blocked as itscontrol voltage will then be equal to its threshold voltage. A reductionof voltage v will cause this control voltage of transistor T to decreasestill further so that transistor T will remain blocked and no dischargeof capacitor C will, as a result, be able to occur.

If now an input voltage v having a value greater than is applied,transistor T, will become conductive, so that the next 1 impulse willcause the control voltage of transistor T to appear, but this timeacross its control electrode 9 and the electrode 5 which will now act asits source. Transistor T will thus be rendered conductive and this willbring about the discharge of capacitor C via the two transistors T and TAs will be appreciated, the above-described elementary circuit may beused as an A.C. to DC. controlled converter when source S, is analternating voltage or bidirectional impulse source.

The bistable set-reset circuit of FIGURES 6 consists of twovoltage-amplifying elementary circuits similar to that shown in FIGURE1, namely T C T and T C T These circuits are supplied by the same sourceS; and are so connected that the input and the output of one circuit maybe respectively connected to the output and to the input of the othercircuit. Further, each of the two circuits comprises a third transistor,respectively T and T connected in parallel to the first transistor,respectively T and T the gate of this third transistor being intendedfor connection to a control voltage, respectively v and v,,'. Thecapacitors C and C are essentially formed by the input capacitance oftransistors T and T respectively.

The operation of this set-reset circuit will readily be understood fromthe explanations given above in connection with the operation of theelementary circuit of FIGURE 1. Depending on whether it is controlvoltage v or v that is being applied, the circuit is placed in one orother of its stable states.

The bistable set-reset circuit of FIGURE 7 differs from that shown inFIGURE 6 in that one of the elementary circuits is of the kind disclosedin our above mentioned patent application Ser. No. 441,975, filed Mar.23, 1965, i.e. one consisting of a transistor T, and of a capacitor C,,the other elementary circuit, i.e. T C T being as before similar to thatshown in FIGURE 1 herein. As in the previous case, each of these twocircuits comprises a further transistor in parallel with the inputtransistor, respectively T and T The circuit operates in a mannersimilar to the FIG- URE 6 circuit except that there is a preferentialstable state, i.e. a stable state to which it will always pass, underthe action of v,,, when both capacitors C and C are discharged. It maybe used with advantage as a memory in a frequency dividing circuit, aswill be explained later.

The frequency dividing stage shown in FIGURE 8 comprises a voltageamplifying circuit T C T similar to that of FIGURE 1, and two elementarycircuits each consisting of a transistor and of a capacitor,respectively T1, C1 and T4, C4.

The input and the output of circuit T C T are respectively connected tothe output of circuit T C and to the input of circuit T C, with theoutput of the latter being connected to the input of circuit T C Thethree circuits are supplied by source S which delivers a periodicvoltage v in the form of trapezoidal impulses. This voltage alsoconstitutes the input voltage v whose frequency is to be divided. Thisfrequency dividing stage operates as follows:

It will be assumed that capacitor C formed by the input capacitance oftransistor T is charged so as to be current conductive, whereastransistor T is blocked.

A voltage v impulse delivered by source S; will cause this voltage v,,to appear at point I, and this in turn will cause transistor T to becomeconductive and cause the discharge of capacitor C via transistors T andT The mutual conductance of transistor T being slight in relation tothat of transistor T the time taken for the discharge of capacitor Cwill be longer than 1 (see FIG- URE 4) so that no voltage will appear atpoint IV, and hence no voltage v will appear at the output 17 of thedividing stage, before the next voltage v impulse. The latter will thuscause the transistor T to become conductive, the transistor T to beblocked, the voltage to appear at point II and the capacitor C to berecharged. The mutual conductance of transistor T being less than thatof transistor T the recharging of capacitor C will take longer than t(FIGURE 4), thereby enabling a voltage v impulse to appear at output 17.

Consequently, as will be apparent from the above, there will only be onevoltage v impulse at the output 17 of the dividin stage for every twovoltage v impulses at the input 21. The frequency of the latter voltageis thus halved.

FIGURES 9a to 9e show, respectively, voltages v V VII: III and rv- Inthis dividing stage, the input (control) voltage v whose frequency is tobe divided, and the supply voltage v are identical. Although thecapacitor C forming the memory of the dividing stage, is not likely tobe prematurely discharged by reverse junction currents when thefrequency is medium or high, the same does not hold true when thefrequency is very low. In this latter case it is necessary to provide asupply current having a frequency greater than that of the controlvoltage so that the capacitor C may be recharged by the supply voltageduring one period of the control voltage.

The dividing stage of FIGURE 10 is for very low frequencies. As will beobserved, this dividing stage comprises a bistable circuit which issimilar to that shown in FIGURE 7 and which consists of two elementarycircuits, the first, which is similar to that of FIGURE 1, comprisingtwo transistors T T and a capacitor C and the second comprising atransistor T and a capacitor C The two circuits are supplied with acommon voltage v provided by a source S The output of the first circuitT C T is, on the one hand, connected to the input of the second circuitT C and is, on the other hand, earthed via a transistor T The gate ofthis transistor T is connected to the output of a third elementarycircuit which comprises a transistor T and a capacitor C and which issupplied by a source S providing the input (control) voltage v The gateof transistor T is connected to the output of the second elementarycircuit T C via a transistor T whose gate is connected to source 8,. Theoutput of this second circuit T C moreover is, on the one hand,connected to the input of the second circuit T C T and is, on the otherhand, earthed via a transistor T whose gate is connected to source S Inthe case under consideration, the frequency of voltage v is twice thatof voltage v This dividing stage operates as follows:

It will be assumed that capacitor C is discharged, so that transistor Tis blocked. A voltage v impulse from source S will cause a fasterincrease of the control voltage of transistor T than that of transistorT Transistor T being then rendered conductive, capacitor C willtherefore remain discharged and transistor T blocked so that voltage 1will appear at point IV and consequently voltage v will appear at theoutput 18 of the dividing stage. This will also result in capacitor Cbeing charged via transistor T and hence in transistor T in becomingconductive. At the next voltage v impulse, which is deliveredsimultaneously with a voltage v impulse, no voltage will appear at pointI since transistor T is conductive. On the other hand, however,transistor T; will become conductive thereby causing transistor T to beblocked. With transistor T also blocked, voltage v will therefore appearat point II, thereby causing capacitor C to be charged via transistor Ttransistor T to become conductive, capacitor C to be discharged viatransistors T and T and transistor T to be blocked. The dividing stagewill remain in this state despite leakage currents since capacitor C isrecharged by the next impulse voltage v At the next impulse of voltage vthe latter will appear at point I since transistor T is blocked. Thiswill cause transistor T and T to become conductive, so that no voltagewill appear at points II and IV and hence at the output 18 of thedividing stage. At the next impulse of v alone, the dividing stage willbe returned to its starting state. Consequently, as will be apparentfrom the above, for every two impulses of voltage v at the input 23there will only be one impulse of voltage v at the output 18 of thedividing stage circuit.

FIGURES 11a to 11 respectively show the voltages 0 e, I, VII III and IV-The two above-described dividing stages, illustrated in FIGURES 8 and 10respectively, each have a dividing factor of two. It is often ofadvantage, when having to divide very high frequencies, to have dividingstages available having a larger dividing factor.

FIGURE 12 shows a frequency dividing stage with which a higher dividingfactor can be obtained. This stage consists of an elementary circuit T CT similar to that of FIGURE 1, and of an elementary circuit T C Theoutput of the first circuit T C T is connected both to the input of atransistor T which grounds the input of the second circuit T C and tothe input of this second circuit via a capacitor C The output of thesecond circuit T C is connected to the input of the first circuit T C TA capacitor C connected in parallel to the input of the second circuit TC is connected to a current source S5, which may, for example, be formedby a cell which is series-connected with a resistor having a high ohmicresistance. The two elementary circuits are supplied by a source 8. ofsinusoidal voltage.

The above-described dividing stage operates as follows:

Let us start from the moment capacitor C is discharged. Transistor Tbeing blocked, voltage v from source 8.; appears at point II, therebyrendering transistor T conductive. No voltage therefore appears at pointIV and hence at output 19 of the dividing stage. The capacitor C is nowbecoming charged by source S As soon as the voltage of capacitor Creaches a value greater than the threshold voltage of T the voltage atpoint II will be sufliciently reduced by the current of transistor TThis will cause the voltage to appear at point IV and hence an increaseof the voltage at point I, via capacitor C thereby helping to chargecapacitor C to a higher voltage. This will cause transistor T to becomefully conductive and transistor T to be blocked. The voltage v whichwill appear at point II will charge capacitor C via transistor T andthis will cause, with a certain time lag, transistor T to becomeconductive and capacitor C to be discharged, i.e. cause the dividingstage to be re turned to the state at which the explanation of itsoperation was started.

FIGURES 13a and 13c respectively show the voltages v v v v and v for thecase in which the dividing factor is 4.

The frequency dividing circuit shown in FIGURE 14 comprises a certainnumber of stages of three different types, i.e. those described withreference to FIGURES 8, 10 and 12. This circuit is intended to reduce ahigh frequency to a very low frequency. The number of stages willobviously depend on the ratio between these two frequencies.

The first stage A of the divider is of the kind illustrated in FIGURE12. It is connected to a source S of direct voltage via a resistor R andto a source S of sinusoidal voltage whose frequency is to be divided.This first stage A is connected to the next stage B, which is of thekind shown in FIGURE 8, via a decoupling circuit which is supplied bysource S and which comprises two seriesmounted transistors T and TT thatare respectively controlled by the voltage of output 19 and by that ofpoint II of stage A (see FIGURE 12), i.e. by phase-shifted impulses. Theconnecting point of transistors T and T is connected to the input ofstage B. The output 17 of the latter is connected to the following stageB which is of the same kind, via a decoupling circuit which comprisestransistors T and T preceded by a voltage-amplifying elementary circuitconsisting of a transistor T and of a capacitor C These two circuitsthus together form a variant of the decoupling circuit which, in fact,is a voltage and power amplifying circuit similar to that disclosed inthe above-mentioned patent specification. Stage B is followed by acertain number of stages of the same kind, connected to one another bythis second decoupling circuit, and the output of the last of thesestages, B is connected via a decoupling circuit T T to the input of astage C of the type illustrated in FIGURE 10. This latter stage isfollowed by a number of stages of the same kind and the output of thelast of these stages, C is connected by the decoupling circuit to theoutput 20 of the divider.

Considering the above explanation about the operation of the FIGURE 1voltageamplifying elementary circuit and about the three types ofdividing stage comprising such a circuit, the operation of theabove-described divider formed thereby will readily be understood. Itshould, however, still be pointed out that the decoupling circuit formedby transistors T and T besides decoupling the input capacitance of onestage from the output of the preceding stage, also acts as a periodicsupply voltage source by converting into such voltage a direct voltagesupplied thereto.

It should further be pointed out that the elementary circuits T Ccomprised by the decoupling circuits of stages B, can be supplieddirectly by source S Clearly, a multi-stage frequency divider could bemade up of a single kind of stage, or of two kinds or also of three, asin the case with the divider described by way of example.

FIGURES 15a to 15f respectively show the voltages 24 11 19 b 17 and s-The described divider only consumes energy for very short periods oftime during which the very low capacitance capacitors of these variousstages are charged. Thus, if the divider stages B all have the samedimensions, the mean power consumption of each of these stages decreaseslinearly with the frequency of its supply voltage. The mean powerconsumption of the divider is thus extremely small.

In view of the ease with which a multi-stage dividing circuit, such asthat just described, can be integrated and of its very low energyconsumption, it can be utilized with advantage in electronic devicesrequiring such fe tures, for instance electronic wrist watches.

Although electronic clocks, in particular clocks comprising a quartzoscillator as a regulator (timing means), and fu1ther comprising anelectronic circuit for dividing the frequency of this oscillator to asuitable value to control a time indicating device, have been known fora long time, no small electronic watch has, as is known, yet beenproduced. This is due to the difficulties involved in economicallyproducing a dividing circuit .of very low energy consumption, whichditficulties have been overcome by the present invention.

Another advantage provided by the abovedescribed divider, due inparticular to the type A stage (FIGURE 12), destines it even more foruse in a small electronic watch. As will have been gathered from theoperation of this stage, the capacitor C is charged and discharged inaccordance with the periodicity of the sinusoidal voltage whilecapacitor C is being charged. When transistor T becomes conductive,capacitor C is charged and discharged during one period of voltage vwhereas capacitor C receives practically no charge at all.

If capacitors C and C both have the same capacitance value, thecapacitive load for source S thus remains practically constant. Thisfact is very important when the periodic voltage source is a highfrequency oscillator, such as, for instance, a quartz oscillator.

The load capacity, which is represented by either of capacitors C and Cmay be included in a circuit tuned to the inherent frequency of thequartz, thereby making it possible to recover the potential energy ofthe charge in these capacitors.

An electronic watch comprising an electronic circuit in accordance withthe present invention, would thus include for source S a small electriccell, and for source S a quartz oscillator supplying a sinusoidalvoltage having, for example, a frequency of about 10 c./s. The dividershown in FIGURE 14 would then be adapted in a 8 manner such that thevoltage at its output 20 may have a frequency of about 1 c./s., so as tobe able to control a time indicating device.

I claim:

1. An integrated electronic circuit consisting essentially ofinsulated-gate field-effect transistors of the same conductivity typeand of capacitor structure electrically connected in a predeterminedcircuit arrangement, each of said transistors having first and secondelectrodes in a conduction path, and a gate electrode for controllingthe conductivity of the path, said electrodes being formed one one faceof a body of semiconductive material and said first and secondelectrodes of the transistors having rectifying junctions with saidbody, and said capacitor structure including a capacitor having firstand second electrodes and a dielectric between said first and secondelectrodes thereof, said capacitor electrodes and dielectric also beingformed on said one face of said body, there being a voltage-amplifyingelementary circuit having therein a pair of said transistors and saidcapacitor, the first electrodes of said pair of transistors and of saidcapacitor being connected to one another, the second electrodes of oneof said pair of transistors and of said capacitor being adapted to beconnected to the terminals of a periodic supply voltage source, the gateelectrode and the second electrode of said one transistor providing theinput of said voltage-amplifying elementary circuit and being adapted tobe connected to the terminals of a control voltage source, the gateelectrode of the other of said pair of transistors being connected tothe second electrode of said capacitor, and the second electrode of saidpair of transistors being in the output of said voltage-amplifyingelementary circuit.

2. An integrated electronic circuit according to claim 1, wherein thesource of periodic supply voltage is a source of unidirectionaltrapezoidal impulses.

3. An integrated electronic circuit according to claim 1 characterizedby being a bistable setreset circuit, having first and second inputs andfirst and second outputs, and comprising a first said voltage-amplifyingelementary circuit formed by first and second said transistors and afirst said capacitor, the first electrodes of said first and secondtransistors and of said first capacitor being connected to one another,the second electrodes of said first transistor and of said firstcapacitor being adapted to be connected to the terminals of a periodicsupply voltage source, the gate electrode and the second electrode ofsaid first transistor providing said first input of said histableset-reset circuit and being adapted to be connected to the terminals ofa control voltage source, the gate electrode of said second transistorbeing connected to the second electrode of said first capacitor, and thefirst and second electrodes of said first transistor providing saidfirst output of said bistable set-reset circuit; a second saidvoltage-amplifying elementary circuit formed by third and fourth saidtransistors and by a second said capacitor, the first electrodes of saidthird and fourth transistors and of said second capacitor beingconnected to one another, the second electrodes of said third transistorand of said second capacitor being adapted to be connected to theterminals of said periodic supply voltage source, the gate electrode andthe second electrode of said third transistor providing said secondinput of said bistable set-reset circuit and being adapted to beconnected to the terminals of a control voltage source, the gateelectrode of said fourth transistor being connected to the secondelectrode of said second capacitor, and the first and second electrodesof said third transistor providing said second output of said bistableset-reset circuit; a fifth said transistor connected in parallel withsaid third transistor, the gate electrode of said fifth transistor beingconnected to the second electrode of said second transistor; and a sixthsaid transistor connected in parallel with said first transistor, thegate electrode of said sixth transistor being connected to the secondelectrode of said fourth transistor.

4. An integrated electronic circuit according to claim 1 characterizedby being a bistable set-reset circuit, having first and second inputsand first and second outputs, and comprising one said voltage-amplifyingelementary circuit formed by first and second said transistors and afirst said capacitor, the first electrodes of said first and secondtransistors and of said first capacitor being connected to one another,the second electrodes of said first transistor and of said firstcapacitor being adapted to be connected to the terminals of a periodicsupply voltage source, the gate electrode and the second electrode ofsaid first transistor providing said first input of said bistableset-reset circuit and being adapted to be connected to the terminals ofa control voltage source, the gate electrode of said second transistorbeing connected to the second electrode of said first capacitor, and thefirst and second electrodes of said first transistor providing saidfirst output of said bistable set-reset circuit; a voltage-amplifyingelementary circuit formed by a third said transistor and a second saidcapacitor, said third transistor and said second capacitor beingconnected in series by their first electrodes, their second electrodesbeing adapted to be connected to the terminals of said periodic supplyvoltage source, the gate electrode and the second electrode of saidthird transistor providing said second input of said bistable set-resetcircuit and being adapted to be connected to the terminals of a controlvoltage source, and the first and second electrodes of said thirdtransistor providing said second output of said bistable set-resetcircuit; a fourth said transistor connected in parallel with said firsttransistor, the gate electrode of said fourth transistor being connectedto the first electrode of said third transistor; and a fifth saidtransistor connected in parallel with said third transistor, the gateelectrode of said fifth transistor being connected to the secondelectrode of said second transistor.

5. An integrated electronic circuit according to claim 1 characterizedby being a frequency dividing circuit comprising, a plurality of stageseach having an input and an output and each including at least one saidvoltageamplifying elementary circuit, and further comprising decouplingmeans connecting the output of one stage with the input of the nextstage, said plurality of stages including at least two of the followingthree types of stage: a low frequency dividing type of stage, a mediumfrequency dividing type of stage and a high frequency dividing type ofstage.

i 6. An integrated electronic circuit according to claim 5, wherein themedium frequency dividing type of stage includes one saidvoltage-amplifying elementary circuit, said one voltage-amplifyingelementary circuit having therein first and second said transistors anda first said capacitor, the first electrodes of said first and secondtransistors and of said first capacitor being connected to one another,the second electrodes of said first transistor and of said firstcapacitor being adapted to be connected to the terminals of a periodicvoltage source; a voltageamplifying elementary circuit having therein athird said transistor and a second said capacitor, said third transistorand said second capacitor being connected in series by their firstelectrodes, their second electrodes being adapted to be connected to theterminals of said periodic voltage source, and the first electrode ofsaid third transistor being connected to the gate electrode of saidfirst transistor; and a further voltage-amplifying elementary circuithaving therein a fourth said transistor and a third said capacitor, saidfourth transistor and said third capacitor being connected in series bytheir first electrodes, their second electrodes being adapted to beconnected to the terminals of said periodic voltage source, the firstelectrode of said fourth transistor being connected to the gateelectrode of said third transistor, and the first and second elecrodesof said fourth transistor providing said output of said medium frequencydividing type of stage.

7. An integrate electronic circuit according to claim 5, wherein eachhigh frequency dividing type of stage includes one saidvoltage-amplifying elementary circuit, said one voltage-amplifyingelementary circuit having therein first and second said transistors anda first said capacitor, the first electrodes of said first and secondtransistors and of said first capacitor being connected to one another,the second electrodes of said first transistor and of said firstcapacitor being adapted to be connected to the terminals of a periodicvoltage source, the gate of said second transistor being connected tothe second electrode of said first capacitor and the first and secondelectrodes of said first transistor providing the output of said highfrequency dividing type of stage; a voltage-amplifying elementarycircuit consisting of a third said transistor and a second saidcapacitor, said third transistor and said second capacitor beingconnected in series by their first electrodes, their second electrodesbeing adapted to be connected to the terminals of said periodic voltagesource, and the first electrode of said third transistor being connectedto the gate electrode of said first transistor; a fourth said transistorof which the first electrode is connected to the gate electrode of saidthird transistor and of which the gate electrode is connected to thesecond electrode of said second transistor; a third said capacitorconnected in parallel with said fourth transistor and being adapted tobe connected to the terminals of a direct voltage source; and a fourthsaid capacitor of which the first electrode is connected to the firstelectrode of said firs transistor and of which the second electrode isconnected to the connection between the gate electrode of said thirdtransistor and the first electrode of said fourth transistor.

8. An integrated electronic circuit according to claim 5, wherein saiddecoupling means comprises a further pair of said transistors which areseries-connected by their first electrodes, their second electrodesbeing adapted to be connected to a direct voltage supply source, theirgate electrodes being connected to the output of said one stage andtheir first electrodes being connected to the input of said next stage.

9. An integrated electronic circuit according to claim 5, wherein saiddecoupling means comprises a further three said transistors and afurther said capacitor, with the first of said further three transistorsand said further capacitor being series-connected by their firstelectrodes, their second electrodes being adapted to be connected to aperiodic voltage supply source, with the second and third of saidfurther three transistors being connected in series by their firstelectrodes, their second electrodes being adapted to be connected to adirect voltage supply source, the gate electrodes of said first andsecond further transistors being connected to the output of said onestage, the gate of said third further transistor being connected to thefirst electrodes of said first further transistor and of said furthercapacitor, and the first electrodes of said second and third furthertransistors being connected to the input of said next stage.

References Cited UNITED STATES PATENTS 6/1964 Luscher 307-88.5 2/1966Heiman 307-885

